1. Technical Field
The present invention relates to integrated circuits in general, and in particular to bi-stable integrated circuits. Still more particularly, the present invention relates to a circuit for filtering single event effect induced glitches.
2. Description of the Prior Art
In certain environments, such as satellite orbital space, in which the level of radiation is relatively intense, electronic devices that utilize static random access memories (SRAMs) are more susceptible to single event upsets (SEUs) or soft errors. These SEUs are typically caused by electron-hole pairs created by, and travelling along the path of, a single energetic particle as it passes through the memory cells of the SRAMs. Should the energetic particle generate a critical charge within a storage node of an SRAM cell, the logic state of the SRAM cell will be upset. Thus, the critical charge is the minimum amount of electrical charge required to change the logic state of the SRAM cell.
Referring now to the drawings and in particular to FIG. 1, there is illustrated a schematic diagram of a conventional memory cell that is typically used in SRAMs. Memory cell 10 is constructed with two cross-coupled complementary metal oxide semiconductor (CMOS) inverters 17 and 18. As shown, inverter 17 includes a p-channel transistor 11 and an n-channel transistor 12, and inverter 18 includes a p-channel transistor 13 and an n-channel transistor 14. The gates of transistors 11 and 12 are connected to the drains of transistors 13 and 14, and the gates of transistors 13 and 14 are connected to the drains of transistors 11 and 12. This arrangement of inverter 17 and inverter 18 is commonly referred to as cross-coupled inverters, and the two lines connecting the gates and the drains of inverters 17 and 18 are commonly referred to as cross-coupling lines. An n-channel pass transistor 15, having its gate connected to a wordline WL, is coupled between a bit line BL and a node S1. Similarly, an n-channel pass transistor 16, also having its gate connected to wordline WL, is coupled between a bit line BL and a node S2. When enabled, pass transistors 15, 16 allow data to pass in and out of memory cell 10 from bit lines BL and BL, respectively. Pass transistors 15, 16 are enabled by wordline WL, which has a state that is a function of the row address within an SRAM. The row address is decoded by a row decoder (not shown) within the SRAM such that only one out of n wordlines is enabled, where n is the total number of rows of memory cells in the SRAM.
During operation, the voltages of nodes S1 and S2 are logical complements of one another, due to the cross-coupling of inverters 17 and 18. When wordline WL is energized by the row decoder according to the row address received, pass transistors 15 and 16 will be turned on, coupling nodes S1 and S2 to bit lines BL and BL, respectively. Accordingly, when wordline WL is high, the state of memory cell 10 can establish a differential voltage on BL and BL.
The logic state of memory cell 10 can be changed by an SEU in many ways. For example, if a single energetic particle, such as a proton particle, strikes the drain of p-channel transistor 11 of inverter 17, electrons will diffuse towards a power supply V.sub.dd of inverter 17, and holes collected at the drain such that the current flows through the PN junction will change the output voltage of inverter 17 at node S1 from a logic low to a logic high when n-channel transistor 12 is on and p-channel transistor 11 is off. However, if the proton particle strikes the drain of n-channel transistor 12 of inverter 17, holes will drift towards ground, and electrons collected at the drain such that the current flows through the PN junction will change the output voltage of inverter 17 at node S1 from a logic high to a logic low when p-channel transistor 11 is on and n-channel transistor 12 is off.
According to the prior art, one method of hardening a memory cell, such as memory cell 10, against SEU is by reducing the amount of charges generated by a given particle strike. This is typically accomplished by using a silicon film thinner than the collection depth in bulk semiconductor. For example, an SRAM cell created on a thin film on an insulator, such as silicon on insulator (SOI), is much less susceptible to SEUs than an SRAM cell created on a bulk silicon because ionization charge along a path in an insulator is more likely to recombine than to be collected compared to ionization charge created in a bulk silicon. However, the processing cost of SOI is much higher than bulk silicon; thus, SOI is generally not the most preferable method. But as the number and density of memory cells and logic circuits within an integrated circuit device have rapidly grown over the years, SEU error rate has become an alarming problem that cannot be ignored, even for application environments in which the level of radiation is relatively low.
Another way to reduce the susceptibility of a memory cell, such as memory cell 10, to SEUs is by increasing the RC time constant of the memory cell. With reference now to FIG. 2, there is illustrated a schematic diagram of an SEU-hardened SRAM cell using a resistive approach, in accordance with the prior art. The SEU hardening scheme for SRAM cell 20 is based on increasing the RC time constant required to produce SEU immunity, and that is accomplished by increasing the resistance of the cross-coupling lines of the cross-coupled inverters from FIG. 1. FIG. 2 illustrates the same circuit as shown in FIG. 1 with the exception that resistors R1 and R2 are included in the cross-coupling lines of inverters 17 and 18. The purpose of resistors R1 and R2 is to increase the RC time constant delay associated with the gate capacitances of transistors 11-14. The initial effect of an energetic particle strike to a node of SRAM cell 20, say node S1, is to change the voltage of node S1. Upset will occur if this voltage change propagates through the cross-coupling of inverters 17 and 18 before the initial voltage of node S1 can be restored. The increased RC delay can slow the feedback propagation through the cross-coupling and allows more time for recovery of the initially affected node S1. But this increase in RC propagation delay also slows the write cycle time of SRAM cell 20. Because the write cycle of SRAMs has typically been faster than the read cycle, some slowing of the write cycle has been viewed as acceptable, especially since the read cycle time is usually more performance critical. However, as memory cells are scaled to smaller geometries, the speed of the write cycle of SRAM cells becomes more critical than in previous SRAM designs. In addition, it is very difficult to control process parameters under the resistive approach. As a result, the resistive approach to SEU hardening is no longer desirable for SRAMs.
Yet another way to reduce the susceptibility of a memory cell to SEU is to increase the capacitance on the drains of inverters 17 and 18 of memory cell 10 from FIG. 1, thus decreasing the voltage change on a node for a given amount of collected charge. Referring now to FIG. 3, there is illustrated a schematic diagram of an SEU-hardened SRAM cell using a capacitive approach in accordance with the prior art. FIG. 3 illustrates the same circuit as shown in FIG. 1 with the exception that a capacitor C is connected across the drains of inverters 17 and 18. By having capacitor C located between the gate and drain of inverters 17 and 18, the effective capacitance is increased by the Miller effect. Also, with capacitor C connected between the gate and drain, a change in the drain voltage will induce a change in the gate voltage such that restoring current is increased. Furthermore, the increased capacitance on the gate will increase the RC delay in the feedback path, thus increasing the resistance to SEUs as well as retarding changes in logic state. However, the capacitive approach to SEU hardening is not very practical because it slows down the speed of the memory cell. Thus, it is desirable to provide an improved SEU hardened memory cell for SRAMs that can easily be fabricated with the conventional complementary metal oxide semiconductor (CMOS) technology.